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description the a1220, a1221, a1222, and a1223 hall-effect sensor ics are extremely temperature-stable and stress-resistant devices especially suited for operation over extended temperature ranges to 150c. superior high-temperature performance is made possible through dynamic offset cancellation, which reduces the residual offset voltage normally caused by device overmolding, temperature dependencies, and thermal stress. each device includes on a single silicon chip a voltage regulator, hall- voltage generator, small-signal amplifier, chopper stabilization, schmitt trigger, and a short-circuit protected open-drain output to sink up to 25 ma. a south pole of sufficient strength turns the output on. a north pole of sufficient strength is necessary to turn the output off. an onboard regulator permits operation with supply voltages of 3 to 24 v. the advantage of operating down to 3 v is that the device can be used in 3-v applications or with additional external resistance in series with the supply pin for greater protection against high voltage transient events. two package styles provide magnetically optimized packages for most applications. package type lh is a modified 3-pin sot23w surface mount package while ua is a three-pin ultra- mini sip for through hole mounting. both packages are lead (pb) free, with 100% matte tin plated leadframes. a1220-ds, rev. 14 features and benefits ? symmetrical latch switchpoints ? resistant to physical stress ? superior temperature stability ? output short-circuit protection ? operation from unregulated supply down to 3 v ? reverse battery protection ? solid-state reliability ? small package sizes chopper stabilized precision hall effect latches packages: functional block diagram not to scale a1220, a1221, a1222, and a1223 3-pin sot23w (suffix lh) (a1223) (a1220, a1221 and a1222) 3-pin sip (suffix ua) regulator gnd vcc vout control current limit dynamic offset cancellation sample and hold to all subcircuits amp low-pass filter
chopper stabilized precision hall effect latches a1220, a1221, a1222, and a1223 2 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com selection guide part number packing 1 mounting ambient, t a b rp (min) b op (max) a1220elhlx-t 13-in. reel, 10000 pieces/reel 3-pin sot23w surface mount ?40oc to 85oc ?40 40 a1220elhlt-t 2 7-in. reel, 3000 pieces/reel 3-pin sot23w surface mount a1220eua-t bulk, 500 pieces/bag 3-pin sip through hole a1220llhlx-t 13-in. reel, 10000 pieces/reel 3-pin sot23w surface mount ?40oc to 150oc a1220llhlt-t 2 7-in. reel, 3000 pieces/reel 3-pin sot23w surface mount a1220lua-t bulk, 500 pieces/bag 3-pin sip through hole a1221elhlx-t 13-in. reel, 10000 pieces/reel 3-pin sot23w surface mount ?40oc to 85oc ?90 90 a1221elhlt-t 2 7-in. reel, 3000 pieces/reel 3-pin sot23w surface mount a1221eua-t bulk, 500 pieces/bag 3-pin sip through hole a1221llhlx-t 13-in. reel, 10000 pieces/reel 3-pin sot23w surface mount ?40oc to 150oc a1221llhlt-t 2 7-in. reel, 3000 pieces/reel 3-pin sot23w surface mount a1221lua-t bulk, 500 pieces/bag 3-pin sip through hole a1222elhlt-t 7-in. reel, 3000 pieces/reel 3-pin sot23w surface mount ?40oc to 85oc ?150 150 a1222elhlx-t 2 13-in. reel, 10000 pieces/reel 3-pin sot23w surface mount a1222eua-t bulk, 500 pieces/bag 3-pin sip through hole a1222llhlt-t 7-in. reel, 3000 pieces/reel 3-pin sot23w surface mount ?40oc to 150oc a1222llhlx-t 2 13-in. reel, 10000 pieces/reel 3-pin sot23w surface mount a1222lua-t bulk, 500 pieces/bag 3-pin sip through hole a1223elhlt-t 7-in. reel, 3000 pieces/reel 3-pin sot23w surface mount ?40oc to 85oc ?180 180 a1223elhlx-t 2 13-in. reel, 10000 pieces/reel 3-pin sot23w surface mount a1223eua-t bulk, 500 pieces/bag 3-pin sip through hole a1223llhlt-t 7-in. reel, 3000 pieces/reel 3-pin sot23w surface mount ?40oc to 150oc a1223llhlx-t 2 13-in. reel, 10000 pieces/reel 3-pin sot23w surface mount a1223lua-t bulk, 500 pieces/bag 3-pin sip through hole 1 contact allegro for additional packing options. 2 available through authorized allegro distributors only.
chopper stabilized precision hall effect latches a1220, a1221, a1222, and a1223 3 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com absolute maximum ratings characteristic symbol notes rating units forward supply voltage v cc 26.5 v reverse supply voltage v rcc ?30 v output off voltage v out 26 v continuous output current i out 25 ma reverse output current i rout ?50 ma operating ambient temperature t a range e ?40 to 85 oc range l ?40 to 150 oc maximum junction temperature t j (max) 165 oc storage temperature t stg ?65 to 170 oc pin-out diagrams terminal list name description number package lh package ua vcc connects power supply to chip 1 1 vout output from circuit 2 3 gnd ground 3 2 1 3 2 gnd vout vcc package ua package lh 1 2 3 gnd vout vcc
chopper stabilized precision hall effect latches a1220, a1221, a1222, and a1223 4 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics valid valid over full operating voltage and ambient temperature ranges; unless otherwise noted characteristics symbol test conditions min. typ. 1 max. unit 2 electrical characteristics forward supply voltage v cc operating, t j < 165c 3 ? 24 v output leakage current i outoff v out = 24 v, b < b rp ??10 a output saturation voltage v out(sat) i out = 20 ma, b > b op ? 185 500 mv output current limit i om b > b op 30 ? 60 ma power-on time 3 t po v cc > 3.0 v, b < b rp (min) ? 10 g, b > b op (max) + 10 g ??25 s chopping frequency f c ? 800 ? khz output rise time 3,4 t r r l = 820 , c l = 20 pf ? 0.2 2 s output fall time 3,4 t f r l = 820 , c l = 20 pf ? 0.1 2 s supply current i cc(on) b > b op , v cc = 12 v ? ? 4 ma i cc(off) b < b rp , v cc = 12 v ? ? 4 ma reverse supply current i rcc v rcc = ?30 v ? ? ?5 ma supply zener clamp voltage v z i cc = 5 ma; t a = 25c 28 ? ? v zener impedance i z i cc = 5 ma; t a = 25c ? 50 ? magnetic characteristics operate point b op a1220 5 22 40 g a1221 15 50 90 g a1222 70 110 150 g a1223 100 150 180 g release point b rp a1220 ?40 ?23 ?5 g a1221 ?90 ?50 ?15 g a1222 ?150 ?110 ?70 g a1223 ?180 ?150 ?100 g hysteresis b hys a1220 (b op ? b rp ) 10 45 80 g a1221 30 100 180 g a1222 140 220 300 g a1223 200 300 360 g 1 typical data are are at t a = 25c and v cc = 12 v, and are for initial design estimations only. 2 1 g (gauss) = 0.1 mt (millitesla). 3 guaranteed by device design and characterization. 4 c l = oscilloscope probe capacitance.
chopper stabilized precision hall effect latches a1220, a1221, a1222, and a1223 5 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com thermal characteristics may require derating at maximum conditions, see application information characteristic symbol test conditions value units package thermal resistance r ja package lh, 1-layer pcb with copper limited to solder pads 228 oc/w package lh, 2-layer pcb with 0.463 in. 2 of copper area each side connected by thermal vias 110 oc/w package ua, 1-layer pcb with copper limited to solder pads 165 oc/w 6 7 8 9 2 3 4 5 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 20 40 60 80 100 120 140 160 180 maximum allowable v cc (v) t j(max) = 165oc; i cc = i cc(max) power derating curve (r q ja = 228 oc/w) package lh, 1-layer pcb (r q ja = 110 oc/w) package lh, 2-layer pcb (r q ja = 165 oc/w) package ua, 1-layer pcb v cc(min) v cc(max) 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 20 40 60 80 100 120 140 160 180 temperature (c) power dissipation, p d (mw) power dissipation versus ambient temperature (r q ja = 165 oc/w) package ua, 1-layer pcb (r q ja = 228 oc/w) package lh, 1-layer pcb (r q ja = 110 oc/w) package lh, 2-layer pcb
chopper stabilized precision hall effect latches a1220, a1221, a1222, and a1223 6 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com average supply current (on) versus temperature 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -60 -40 -20 0 20 40 60 80 100 120 140 160 t a (c) i cc(av) (ma) average supply current (on) versus supply voltage 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2 6 10 14 18 22 26 v cc (v) icc (av) (ma) average supply current (off) versus temperature 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -60 -40 -20 0 20 40 60 80 100 120 140 160 t a (c) i cc(av) (ma) average supply current (off) versus supply voltage 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2 6 10 14 18 22 26 v cc (v) icc (av) (ma) saturation voltage versus temperature 0 50 100 150 200 250 300 -60 -40 -20 0 20 40 60 80 100 120 140 160 t a (c) v out(sat) (mv) 2.6v 3.0v 3.8v 4.2v 12v 24v saturation voltage vers us supply voltage 0 50 100 150 200 250 300 0 2 4 6 8 101214161820222426 v cc (v) v out(sat) (mv) 3.0v 3.8v 4.2v 12v 24v 150c -40c 25c 150c -40c 25c 150c -40c 25c 3.0v 3.8v 4.2v 12v 24v characteristic performance a1220, a1221, a1222, and a1223 electrical characteristics
chopper stabilized precision hall effect latches a1220, a1221, a1222, and a1223 7 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 150 -40 25 (c) 150 -40 25 (c) 150 -40 25 (c) operate point versus temperature 0 5 10 15 20 25 30 35 40 -60 -40 -20 0 20 40 60 80 100 120 140 160 t a (c) b op (g) 3.0 3.8 4.2 12 24 operate point versus supply voltage 0 5 10 15 20 25 30 35 40 2 6 10 14 18 22 26 v cc (v) b op (g) release point versus temperature -40 -35 -30 -25 -20 -15 -10 -5 0 -60 -40 -20 0 20 40 60 80 100 120 140 160 t a (c) b rp (g) 3.0 3.8 4.2 12 24 release point versus supply voltage -40 -35 -30 -25 -20 -15 -10 -5 0 2 6 10 14 18 22 26 v cc (v) b rp (g) switchpoint hysteresis versus temperature 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 -60 -40 -20 0 20 40 60 80 100 120 140 160 t a (c) b hys (g) 3.0 3.8 4.2 12 24 switchpoint hysteresis versus supply voltage 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 2 6 10 14 18 22 26 v cc (v) b hys (g) (v) (v) (v) a1220 magnetic characteristics
chopper stabilized precision hall effect latches a1220, a1221, a1222, and a1223 8 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com operate point versus temperature 90 80 70 60 50 40 30 20 10 0 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -60 -40 -20 0 20 40 60 80 100 120 140 160 t a (c) b op (g) operate point versus supply voltage 90 80 70 60 50 40 30 20 10 0 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 2 6 10 14 18 22 26 v cc (v) b op (g) release point versus temperature -60 -40 -20 0 20 40 60 80 100 120 140 160 t a (c) b rp (g) release point versus supply voltage 2 6 10 14 18 22 26 v cc (v) b rp (g) switchpoint hysteresis versus temperature 180 170 160 150 140 130 120 110 100 90 80 70 60 50 40 30 -60 -40 -20 0 20 40 60 80 100 120 140 160 t a (c) b hys (g) switchpoint hysteresis versus supply voltage 2 6 10 14 18 22 26 v cc (v) b hys (g) 180 170 160 150 140 130 120 110 100 90 80 70 60 50 40 30 2.6 12 24 (v) 2.6 12 24 (v) 2.6 12 24 (v) 150 -40 25 (c) 150 -40 25 (c) 150 -40 25 (c) a1221 magnetic characteristics
chopper stabilized precision hall effect latches a1220, a1221, a1222, and a1223 9 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com operate point versus temperature 150 140 130 120 110 100 90 80 70 -70 -80 -90 -100 -110 -120 -130 -140 -150 -60 -40 -20 0 20 40 60 80 100 120 140 160 t a (c) b op (g) operate point versus supply voltage 180 170 160 150 140 130 120 110 100 90 80 70 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 2 6 10 14 18 22 26 v cc (v) b op (g) release point versus temperature -60 -40 -20 0 20 40 60 80 100 120 140 160 t a (c) b rp (g) release point versus supply voltage 2 6 10 14 18 22 26 v cc (v) b rp (g) switchpoint hysteresis versus temperature 300 280 260 240 220 200 180 160 140 -60 -40 -20 0 20 40 60 80 100 120 140 160 t a (c) b hys (g) switchpoint hysteresis versus supply voltage 2 6 10 14 18 22 26 v cc (v) b hys (g) 300 280 260 240 220 200 180 160 140 2.6 24 (v) 2.6 24 (v) 2.6 24 (v) 150 -40 25 (c) 150 -40 25 (c) 150 -40 25 (c) a1222 magnetic characteristics
chopper stabilized precision hall effect latches a1220, a1221, a1222, and a1223 10 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com c byp a122x vout gnd 0.1 f vcc output r l v s operation the output of these devices switches low (turns on) when a mag- netic field perpendicular to the hall element exceeds the operate point threshold, b op (see panel a of figure 1). after turn-on, the output voltage is v out(sat) . the output transistor is capable of sinking current up to the short circuit current limit, i om , which is a minimum of 30 ma. when the magnetic field is reduced below the release point, b rp , the device output goes high (turns off). the difference in the magnetic operate and release points is the hysteresis, b hys , of the device. this built-in hysteresis allows clean switching of the output even in the presence of external mechanical vibration and electrical noise. removal of the magnetic field will leave the device output latched on if the last crossed switchpoint is b op , or latched off if the last crossed switch point is b rp . powering-on the device in the hysteresis range (less than b op and higher than b rp ) will give an indeterminate output state. the cor- rect state is attained after the first excursion beyond b op or b rp . applications it is strongly recommended that an external bypass capacitor be connected (in close proximity to the hall element) between the supply and ground of the device to reduce both external noise and noise generated by the chopper stabilization technique. as is shown in panel b of figure 1, a 0.1 f capacitor is typical. extensive applications information for hall effect devices is available in: ? hall-effect ic applications guide , application note 27701 ? guidelines for designing subassemblies using hall-effect devices , application note 27703.1 ? soldering methods for allegro?s products ? smt and through- hole , application note 26009 all are provided in allegro electronic data book , ams-702, and the allegro web site, www.allegromicro.com. figure 1. switching behavior of latches. in panel a, on the horizontal axis, the b+ direction indicates increasing south polari ty magnetic field strength, and the b? direction indicates decreasing south polarity field strength (including the case of increasing north polarity). this behavior can be exhibited when using a circuit such as that shown in panel b. (a) (b) functional description b op b rp b hys v cc v out v out(sat) switch to low switch to high b+ b? v+ 0 0
chopper stabilized precision hall effect latches a1220, a1221, a1222, and a1223 11 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com amp regulator clock/logic hall element sample and hold low-pass filter chopper stabilization technique when using hall effect technology, a limiting factor for switchpoint accuracy is the small signal voltage developed across the hall element. this voltage is disproportionally small relative to the offset that can be produced at the output of the hall ele- ment. this makes it difficult to process the signal while main- taining an accurate, reliable output over the specified operating temperature and voltage ranges. chopper stabilization is a unique approach used to minimize hall offset on the chip. the patented allegro technique, namely dynamic quadrature offset cancellation, removes key sources of the output drift induced by thermal and mechanical stresses. this offset reduction technique is based on a signal modulation- demodulation process. the undesired offset signal is separated from the magnetic field-induced signal in the frequency domain, through modulation. the subsequent demodulation acts as a modulation process for the offset, causing the magnetic field induced signal to recover its original spectrum at baseband, while the dc offset becomes a high-frequency signal. the magnetic sourced signal then can pass through a low-pass filter, while the modulated dc offset is suppressed. this configuration is illus- trated in figure 2. the chopper stabilization technique uses a 400 khz high fre- quency clock. for demodulation process, a sample and hold technique is used, where the sampling is performed at twice the chopper frequency (800 khz). this high-frequency operation allows a greater sampling rate, which results in higher accuracy and faster signal-processing capability. this approach desensi- tizes the chip to the effects of thermal and mechanical stresses, and produces devices that have extremely stable quiescent hall output voltages and precise recoverability after temperature cycling. this technique is made possible through the use of a bicmos process, which allows the use of low-offset, low-noise amplifiers in combination with high-density logic integration and sample-and-hold circuits. the repeatability of magnetic field-induced switching is affected slightly by a chopper technique. however, the allegro high frequency chopping approach minimizes the affect of jitter and makes it imperceptible in most applications. applications that are more likely to be sensitive to such degradation are those requiring precise sensing of alternating magnetic fields; for example, speed sensing of ring-magnet targets. for such applications, allegro recommends its digital device families with lower sensitivity to jitter. for more information on those devices, contact your allegro sales representative. figure 2. model of chopper stabilization technique
chopper stabilized precision hall effect latches a1220, a1221, a1222, and a1223 12 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com power derating the device must be operated below the maximum junction temperature of the device, t j(max) . under certain combinations of peak conditions, reliable operation may require derating supplied power or improving the heat dissipation properties of the appli- cation. this section presents a procedure for correlating factors affecting operating t j . (thermal data is also available on the allegro microsystems website.) the package thermal resistance, r ? ja , is a figure of merit sum- marizing the ability of the application and the device to dissipate heat from the junction (die), through all paths to the ambient air. its primary component is the effective thermal conductivity, k, of the printed circuit board, including adjacent devices and traces. radiation from the die through the device case, r ? jc , is relatively small component of r ? ja . ambient air temperature, t a , and air motion are significant external factors, damped by overmolding. the effect of varying power levels (power dissipation, p d ), can be estimated. the following formulas represent the fundamental relationships used to estimate t j , at p d . p d = v in i in (1) ? ???????????????????????? t = p d r ? ja (2) t j = t a + t (3) for example, given common conditions such as: t a = 25c, v cc = 12 v, i cc = 1.6 ma, and r ? ja = 165 c/w, then: p d = v cc i cc = 12 v 1.6 ma = 19 mw ?? t = p d r ? ja = 19 mw 165 c/w = 3c t j = t a + ? t = 25c + 3c = 28c a worst-case estimate, p d(max) , represents the maximum allow- able power level (v cc(max) , i cc(max) ), without exceeding t j(max) , at a selected r ? ja and t a . example : reliability for v cc at t a = 150c, package lh, using a minimum-k pcb. observe the worst-case ratings for the device, specifically: r ? ja = 228c/w, t j (max) = 165c, v cc (max) = 24 v, and i cc (max) = 4 ma. calculate the maximum allowable power level, p d (max). first, invert equation 3: ? t max = t j (max) ? t a = 165 c ? 150 c = 15 c this provides the allowable increase to t j resulting from internal power dissipation. then, invert equation 2: ???? p d (max) = ? t max r ? ja = 15c 228 c/w = 66 mw finally, invert equation 1 with respect to voltage: v cc(est) = p d (max) i cc (max) = 66 mw 4 ma = 16.4 v the result indicates that, at t a , the application and device can dissipate adequate amounts of heat at voltages v cc(est) . compare v cc(est) to v cc (max). if v cc(est) v cc (max), then reli- able operation between v cc(est) and v cc (max) requires enhanced r ? ja . if v cc(est) v cc (max), then operation between v cc(est) and v cc (max) is reliable under these conditions.
chopper stabilized precision hall effect latches a1220, a1221, a1222, and a1223 13 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 0.55 ref gauge plane seating plane 0.25 bsc 0.95 bsc 0.95 1.00 0.70 2.40 2 1 a active area depth, 0.28 mm ref b c b reference land pattern layout all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances branding scale and appearance at supplier discretion a pcb layout reference view branded face c standard branding reference view n = last two digits of device part number t = temperature code (letter) 1 nnt n = last three digits of device part number 1 nnn 2.90 +0.10 ?0.20 44 8x 10 ref 0.180 +0.020 ?0.053 0.05 +0.10 ?0.05 0.25 min 1.91 +0.19 ?0.06 2.98 +0.12 ?0.08 1.00 0.13 0.40 0.10 for reference only; not for tooling use (reference dwg. 802840) dimensions in millimeters dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown d hall element, not to scale d d d 1.49 0.96 3 package lh, 3-pin (sot-23w) a1220 and a1221 only a1220, a1221, a1222, and a1223
chopper stabilized precision hall effect latches a1220, a1221, a1222, and a1223 14 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package ua, 3-pin sip (a1220, a1221, and a1222) 23 1 0.79 ref 1.27 nom 2.16 max 0.51 ref 45 c 45 b e e e 2.04 1.44 gate burr area a b c dambar removal protrusion (6x) a d e d branding scale and appearance at supplier discretion hall element, not to scale active area depth, 0.50 mm ref for reference only; not for tooling use (reference dwg-9049) dimensions in millimeters dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown standard branding reference view = supplier emblem n = last two digits of device part number t = temperature code nnt 1 mold ejector pin indent branded face 4.09 +0.08 ?0.05 0.41 +0.03 ?0.06 3.02 +0.08 ?0.05 0.43 +0.05 ?0.07 15.75 0.51 1.52 0.05
chopper stabilized precision hall effect latches a1220, a1221, a1222, and a1223 15 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package ua, 3-pin sip (a1223) 23 1 1.27 nom 1.02 max 45 45 c 1.52 0.05 b gate and tie bar burr area a b c dambar removal protrusion (6x) a d e e e 1.44 2.04 e active area depth, 0.50 mm ref branding scale and appearance at supplier discretion hall element (not to scale) for reference only; not for tooling use (reference dwg-9065) dimensions in millimeters dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown mold ejector pin indent d standard branding reference view = supplier emblem n = last three digits of device part number nnn 1 0.41 +0.03 ?0.06 0.43 +0.05 ?0.07 14.99 0.25 4.09 +0.08 ?0.05 3.02 +0.08 ?0.05 0.79 ref 10 branded face
chopper stabilized precision hall effect latches a1220, a1221, a1222, and a1223 16 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com copyright ?2009-2012, allegro microsystems, inc. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. for the latest version of this document, visit our website: www.allegromicro.com revision history revision current revision date description of revision rev. 14 july 12, 2012 update ua package drawing

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